we relentlessly strive to create products that enrich peoples lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out..
Description
In this role, you will be responsible for developing and owning IP level Netlist generation (Synthesis, UPF , scan insertion, external IPs integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign-off the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
Description
In this role, you will be responsible for developing and owning IP level Netlist generation (Synthesis, UPF , scan insertion, external IPs integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign-off the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
Requirements:
Knowledge of the ASIC design timing closure flow and methodology.
Expertise in STA tools (Primetime) and flow generation.
5+ years of experience in the field.
At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure.
Preferred Qualifications
Understanding of timing corners/modes.
Familiarity with process variations and signal integrity-related issues.
Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl).
Knowledge of synthesis, DFT, and backend-related methodologies and tools.
Strong communication skills, as you will interact with various groups.
Knowledge of the ASIC design timing closure flow and methodology.
Expertise in STA tools (Primetime) and flow generation.
5+ years of experience in the field.
At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure.
Preferred Qualifications
Understanding of timing corners/modes.
Familiarity with process variations and signal integrity-related issues.
Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl).
Knowledge of synthesis, DFT, and backend-related methodologies and tools.
Strong communication skills, as you will interact with various groups.
This position is open to all candidates.
