We are looking for a highly experienced Logic Design Engineer who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding experienced DevOps Engineer customer base.
Join us in this exciting journey to redefine the future of quantum computing.
Responsibilities:
Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation).
Join us in this exciting journey to redefine the future of quantum computing.
Responsibilities:
Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation).
Requirements:
BSc in electrical/computer engineering or relevant military background- Must
At least 7 years of experience- Must
Proven track record in RTL coding with System Verilog- Must
Experience with System Verilog- Must
VCS, Vivado – Advantage.
BSc in electrical/computer engineering or relevant military background- Must
At least 7 years of experience- Must
Proven track record in RTL coding with System Verilog- Must
Experience with System Verilog- Must
VCS, Vivado – Advantage.
This position is open to all candidates.
