We are expanding our Design Verification team, and invite you to explore Space with us! The job includes taking a viable role in the VLSI verification tasks of our line of products.
What you will be doing:
Plan & implement UVM verification environments.
Interact with Architecture, Design, SW and Validation teams.
Define new DV methodologies and improve existing ones.
Work on both ASIC and FPGA Space system projects.
Requirements:
5+ years of relevant design verification experience.
Proficiency in System Verilog UVM.
5+ years of relevant design verification experience.
Proficiency in System Verilog UVM.
This position is open to all candidates.
