Our DDR SoC team is looking for an experienced verification engineer to be involved in the development of our current and future SoC.
Working on the cutting-edge technologies to deliver our EyeQ SoC family for ADAS and autonomous vehicles.
What will your job look like:
Verify the SoC DDR interface including the integration of advanced DDR controller and PHY.
Build block level Verification of the DDR interface
VIP integration for interface protocols and DDR.
Collaborate with designers, architects and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Write and debug tests that combine UVM methodology and SW code.
Define, develop, and execute complex verification scenarios on the DDR interface.
Working on the cutting-edge technologies to deliver our EyeQ SoC family for ADAS and autonomous vehicles.
What will your job look like:
Verify the SoC DDR interface including the integration of advanced DDR controller and PHY.
Build block level Verification of the DDR interface
VIP integration for interface protocols and DDR.
Collaborate with designers, architects and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Write and debug tests that combine UVM methodology and SW code.
Define, develop, and execute complex verification scenarios on the DDR interface.
Requirements:
BSc in electrical engineering, computer engineering, or computer science
3+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++)
Knowledge in Industry Standard protocols such as AXI/OCP/APB
3rd-party IPs integration testing experience including use of VIPs
System Verilog writing skills, preferably in OVM/UVM
Technical knowledge of DDR/LPDDR interface – Advantage.
BSc in electrical engineering, computer engineering, or computer science
3+ years of experience working in verification environment, tests, and test bench development (SV/UVM/C/C++)
Knowledge in Industry Standard protocols such as AXI/OCP/APB
3rd-party IPs integration testing experience including use of VIPs
System Verilog writing skills, preferably in OVM/UVM
Technical knowledge of DDR/LPDDR interface – Advantage.
This position is open to all candidates.
