Define, plan and implement our next chip in on-going product line and in a new product line oF cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.
Requirements:
BSc or MSc?in Electrical Engineering?or Computer Engineering
8+?years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
Preferred
Networking design experience Major Advantage
backend experience: STA tools, formal equivalence tools, frontend / backend handoff methodologies.
SOC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, PERL, Tcl, Python, Make, and automation methods/algorithms.
BSc or MSc?in Electrical Engineering?or Computer Engineering
8+?years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
Preferred
Networking design experience Major Advantage
backend experience: STA tools, formal equivalence tools, frontend / backend handoff methodologies.
SOC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, PERL, Tcl, Python, Make, and automation methods/algorithms.
This position is open to all candidates.
