Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.
Requirements:
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (Alternatively, exceptional proven track record in similar tasks)
5+ years of experience in one or more of following disciplines: definition of CPU architectural features, HW/SW co-design (or SW defined HW), Low level performance profiling and optimization of SW with exposure to CPU ISA.
Fluent spoken and written English
Behavioral skills: Team player. Although this is not for a manager position, we require interpersonal skills needed to lead partners and colleagues towards achieving a technical goal
Advantageous qualifications:
Familiarity with dense compute workloads and analysis (e.g., AI, HPC, financial, etc.)
Familiarity with Vector Architectures.
BSc or higher degree in Computer Science/Engineering or related discipline from a leading university. (Alternatively, exceptional proven track record in similar tasks)
5+ years of experience in one or more of following disciplines: definition of CPU architectural features, HW/SW co-design (or SW defined HW), Low level performance profiling and optimization of SW with exposure to CPU ISA.
Fluent spoken and written English
Behavioral skills: Team player. Although this is not for a manager position, we require interpersonal skills needed to lead partners and colleagues towards achieving a technical goal
Advantageous qualifications:
Familiarity with dense compute workloads and analysis (e.g., AI, HPC, financial, etc.)
Familiarity with Vector Architectures.
This position is open to all candidates.
