As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing.
Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Requirements:
Minimum Qualifications
5+ years of work experience.
Knowledge of the ASIC design timing closure flow and methodology.
At least 2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow.
Knowledge of Timing corners/ modes.
Hands on experience in Timing / SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) Familiarity with synthesis, DFT and backend related methodology and tools.
Minimum Qualifications
5+ years of work experience.
Knowledge of the ASIC design timing closure flow and methodology.
At least 2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow.
Knowledge of Timing corners/ modes.
Hands on experience in Timing / SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) Familiarity with synthesis, DFT and backend related methodology and tools.
Preferred Qualifications
B.Sc / M.Sc in Electrical or Computer Engineering.
This position is open to all candidates.
