We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.
Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.
Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.
Requirements:
6+ years of verification experience, including hands-on experience building complex environments from scratch
Advanced knowledge of verification flow, SOC architecture and design
Expertise in verification languages such as SystemVerilog, UVM, Spaceman
Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug
Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy
Bachelor degree in electrical engineering or computer science, or equivalent experience.
6+ years of verification experience, including hands-on experience building complex environments from scratch
Advanced knowledge of verification flow, SOC architecture and design
Expertise in verification languages such as SystemVerilog, UVM, Spaceman
Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug
Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy
Bachelor degree in electrical engineering or computer science, or equivalent experience.
This position is open to all candidates.
