As a DV Lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute UVM‑based verification strategy, and lead a small team of talented engineers to first‑time‑right silicon.
This is a 5 days on site position in Haifa
What youll do
Define verification strategy, test plan, and coverage goals for complex peripheral IP and subsystem blocks
Architect, develop, and maintain UVM‑based constrained‑random verification environments
Lead day‑to‑day activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance
Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams
Analyze and close functional and code coverage, drive quality metrics to tape‑out criteria
Contribute to methodology and flow improvements across the Peripheral DV team
BSc/MSc in Electrical/Computer Engineering or related field
At least 7 years of hands‑on verification experience using UVM and SystemVerilog
Strong background in digital design and SoC/IP architecture
Proven technical leadership:
Prior experience leading or mentoring engineers or
Demonstrated ability and motivation to lead a small DV team (e.g., ownership of major IP, driving cross‑functional efforts)
High technical proficiency in:
UVM testbench architecture (agents, sequences, scoreboards, coverage)
Constrained‑random, coverage‑driven verification
Debugging complex failures in large‑scale regressions
Scripting (Python/Perl/Tcl/shell) in a UNIX/Linux environment
