Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.
Requirements:
Basic Qualifications
– 8+ years of experience in physical design.
– Understanding the entire place and route flow (RTL to GDS).
– Very deep understanding of timing.
– Process and technology (advanced nodes) oriented.
– Leadership and mentoring skills.
Basic Qualifications
– 8+ years of experience in physical design.
– Understanding the entire place and route flow (RTL to GDS).
– Very deep understanding of timing.
– Process and technology (advanced nodes) oriented.
– Leadership and mentoring skills.
Preferred Qualifications
– Full-chip experience (floor plan, layout, timing).
– Previous experience in high-speed designs, multi-voltage (low power) designs.
This position is open to all candidates.
