Senior Asic Design
we are looking for a Senior Asic Design.Your Impact:Write and review micro-architecture specificationsImplement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirementsContribute to full chip integration, timing methodology, and analysisCollaborate with verification engineers to resolve bugs and achieve coverage closureWork with the physical design team to close timing and PnR issuesSupport design methodology evolution and … Read more








