What you will be doing:
Define formal verification flows and requirements for security features.
Identify key security behaviors for verification to write clear testplans for complex designs.
Implement testplans using the latest formal techniques, including the development of environment assumptions, assertions, and cover properties.
Drive verification of hardware features that improve security of our chips.
Use black-boxing, proof decompositions and abstractions to overcome complexity challenges and obtain full proofs, or bounded proofs with sufficient coverage.
Drive FV tools to realize their best performance.
Debug RTL to identify causes of failure scenarios.
Contribute to the flow and script development to improve team efficiency.
Articulate the security FV coverage to the design, simulation and architecture teams.
What we need to see:
14+ years of experience in FV, including 5 years in applying FV to hardware security, experience with verification of security scenarios (key leakage, corruption, etc.).
Background with micro-architectural attacks.
Strong analytical skills to solve complex problems.
Knowledge of FV methodologies and techniques.
Able to implement abstraction techniques for effective verification.
Hands-on experience with Verilog / SystemVerilog HDLs, and ability to understand complex RTL quickly.
Excellent command of scripting using TCL, Perl, and Python.
Experience with commercial FV tools (e.g. Jasper, VC Formal )
Experience with commercial security FV tools (e.g. Jasper SPV, VC Formal FSV or Cycuity)
Excellent interpersonal skills, able to effectively collaborate and work with members of a distributed team.
