We are looking for a Verification Engineer.
The role Includes:
Develop ASIC verification environment for full chip (Soc) and unit levels (IPs).
Development of System Verilog, UVM based protocol components from drivers, monitors, checkers up to coverage monitors.
Responsibility for generation and execution of verification plan for challenging digital blocks.
Independent and initiative engineers to learn and work with great teammates.
The role Includes:
Develop ASIC verification environment for full chip (Soc) and unit levels (IPs).
Development of System Verilog, UVM based protocol components from drivers, monitors, checkers up to coverage monitors.
Responsibility for generation and execution of verification plan for challenging digital blocks.
Independent and initiative engineers to learn and work with great teammates.
Requirements:
B.Sc. in Electrical Engineering from Well-known leading academic institute.
Minimum of 7 years of experience in verification from semiconductor companies.
Demonstrated experience in building a complicated verification environment
Knowledge and experience in standard verification methodologies such as UVM/OVM
Knowledge in Formal verification and Emulation- an advantage
Knowledge in scripting languages such as Python or Perl- an advantage
Very good communication skills
B.Sc. in Electrical Engineering from Well-known leading academic institute.
Minimum of 7 years of experience in verification from semiconductor companies.
Demonstrated experience in building a complicated verification environment
Knowledge and experience in standard verification methodologies such as UVM/OVM
Knowledge in Formal verification and Emulation- an advantage
Knowledge in scripting languages such as Python or Perl- an advantage
Very good communication skills
This position is open to all candidates.
