Required Senior Verification Engineer – Silicon One
Job Description
Meet the Team
Join the Silicon One Front-End Design Verification team, responsible for validating the most advanced networking silicon in the world. Our team ensures functional correctness, quality, and reliability across the entire design flow. We combine state-of-the-art methodologies with a collaborative, startup-like culture, while being backed by our stability and resources.
Your Impact:
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure.
Job Description
Meet the Team
Join the Silicon One Front-End Design Verification team, responsible for validating the most advanced networking silicon in the world. Our team ensures functional correctness, quality, and reliability across the entire design flow. We combine state-of-the-art methodologies with a collaborative, startup-like culture, while being backed by our stability and resources.
Your Impact:
Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure.
Requirements:
Minimum Qualifications
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
Preferred Qualifications
Scripting skills (Python, Perl, TCL, or shell)
Experience with system-level integration (AMBA, PCIe, SPI, I2C, JTAG, CPU)
Basic software knowledge (driver-level)
Basic design knowledge and familiarity with CDC concepts.
Minimum Qualifications
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
Preferred Qualifications
Scripting skills (Python, Perl, TCL, or shell)
Experience with system-level integration (AMBA, PCIe, SPI, I2C, JTAG, CPU)
Basic software knowledge (driver-level)
Basic design knowledge and familiarity with CDC concepts.
This position is open to all candidates.
