As a DFT Engineer at Annapurna Labs (AWS), you'll take ownership of testability architectures and DFT logic, driving their development and verification through the full hardware lifecycle. Your responsibilities may include:
Define and implement DFT architectures for complex SoC designs.
Develop and integrate DFT logic including: MBIST (Memory Built-In Self-Test), JTAG/TAP, and boundary scan.
RTL coding and debug of DFT controllers and infrastructure using Verilog/SystemVerilog.
Drive gate-level simulations to validate DFT functionality and test patterns.
Develop and verify DFT logic using UVM-based testbenches, functional simulation, and coverage-driven verification.
Participate in design reviews, DFT sign-off processes, and tapeout preparation
Cross-functional collaboration with Design, Verification, Physical Design, and Production/Test teams.
Define and implement DFT architectures for complex SoC designs.
Develop and integrate DFT logic including: MBIST (Memory Built-In Self-Test), JTAG/TAP, and boundary scan.
RTL coding and debug of DFT controllers and infrastructure using Verilog/SystemVerilog.
Drive gate-level simulations to validate DFT functionality and test patterns.
Develop and verify DFT logic using UVM-based testbenches, functional simulation, and coverage-driven verification.
Participate in design reviews, DFT sign-off processes, and tapeout preparation
Cross-functional collaboration with Design, Verification, Physical Design, and Production/Test teams.
Requirements:
Basic Qualifications
– Hands-on experience in RTL design using Verilog/System Verilog.
– Experience with chip design flows and gate-level simulations.
Basic Qualifications
– Hands-on experience in RTL design using Verilog/System Verilog.
– Experience with chip design flows and gate-level simulations.
Preferred Qualifications
– Experience with DFT design and implementation (MBIST, JTAG/IEEE 1149.1, memory repair flows) and familiarity with industry-standard EDA tools such as Synopsys DFT Compiler and Tessent.
– Verification background including UVM testbenches, coverage-driven verification, FPGA, and emulator environments, with advanced scripting skills in Perl, Tcl, and/or Python.
– End-to-end chip development experience- from RTL design through synthesis, timing analysis, and physical design constraints to post-silicon validation, production, and memory fault debugging.
This position is open to all candidates.
