What you'll be doing:
You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.
Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.
Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.
We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.
A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.
Proficiency using Python, Tcl, Shell, Make scripting.
Experience in Linux environments.
AI tools orientation or alternatively a desire to learn.
Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).
Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)
Self-motivation, attention to detail, and good interpersonal skills.
Ways to stand out from the crowd:
Experience with data collection and analysis
Experience in methodology definition / flow owner of Full-chip / Place and Route
Great teammate.
Ownership, self-learning skills, and ability to work autonomously.
