Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.
Responsibilities:
Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc).
Full block level timing closure and manufacturing checks signoff including power planning and analysis.
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level.
Insertion of DFT test structures and chip level integration, capture and simulation.
Jointly with management, build your career development and growth opportunities.
Requirements:
Bachelor of Science in Electrical Engineering, Computer Science, or related field from a major academic institute.
At least 8 years' experience as Physical Design Engineer.
Experience with COT/ASIC physical design flow covering: Synthesis, Floor-planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation.
Deep sub-micron (28nm or below) process technologies
Industry standard design processes for deep sub-micron designs
Problem-solving and analytical skills
Practical use of scripting languages Tcl/Python/Perl etc.
Experience of at least one of the following EDA tool flows: Cadence or Synopsys.
Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow.
Managing/Interfacing to sub-contract design service providers.
Bachelor of Science in Electrical Engineering, Computer Science, or related field from a major academic institute.
At least 8 years' experience as Physical Design Engineer.
Experience with COT/ASIC physical design flow covering: Synthesis, Floor-planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation.
Deep sub-micron (28nm or below) process technologies
Industry standard design processes for deep sub-micron designs
Problem-solving and analytical skills
Practical use of scripting languages Tcl/Python/Perl etc.
Experience of at least one of the following EDA tool flows: Cadence or Synopsys.
Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow.
Managing/Interfacing to sub-contract design service providers.
This position is open to all candidates.
