This is an RTL design role, not a circuit or transistor-level design role. You will translate micro-architecture specifications into high-quality synthesizable RTL, and drive that RTL through to silicon in close partnership with the micro-architecture, Design Verification, and Physical Design (backend) teams. You will also interact with CAD, Package Design, Software, and DFT teams.
What you'll be doing:
Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out.
Defining and implementing the SOC clock and reset architecture together with the micro-architecture team – collecting clocking requirements from every unit on the chip and turning them into a coherent, verifiable design.
Owning clock domain crossing infrastructure and CDC closure across the SOC.
Partnering with the micro-architecture team to review specifications, close on design intent, and provide feedback on implementation cost, timing, area, and power.
Working hand-in-hand with the Physical Design (backend) team on clock tree implementation and constraints, partitioning, floorplan and timing feedback, trial synthesis, congestion and timing convergence, and physical design readiness.
Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows.
Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks.
Supporting SOC-level chip build and assembly, and developing/deploying automation flows that make RTL integration and design quality checking repeatable and scalable.
Supporting emulation, firmware, and post-silicon bring-up customers of your design.
What we need to see:
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
3+ years of relevant experience in RTL/logic design.
Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation.
Experience taking a design from micro-architecture specification through verification and physical implementation.
Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing.
Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis).
Great teammate with strong communication skills across micro-architecture, DV, and backend teams.
Ways to stand out from the crowd:
Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customers.
Prior ownership of SOC-level clocking or reset architecture on a taped-out chip.
Experience with PLL/clock generator integration and clock tree constraint development with backend teams.
