our company is a leading supplier of custom SOC and security hardware solutions for the computing and server markets. We are looking for a highly experienced CAD Engineer from the semiconductor industry to join Nuvoton as a key contributor. In this role, you will help modernize and upgrade our design environment, EDA infrastructure, and in-house CAD tools to support advanced technology nodes, improve engineering efficiency, and enable future growth. You will also play a key role in supporting the design and verification activities of current and future semiconductor projects.
Requirements:
* B.Sc. / M.Sc. in Computer Science, Electrical Engineering, or a related field from a leading institute.
* Strong programming and scripting skills in C / C ++, TCL, Python, and Linux shell scripting.
* Experience leveraging Generative AI tools for software development, automation, and productivity enhancement.
* Solid understanding of IC design and verification flows, with at least 5 years of hands-on experience using semiconductor EDA tools from Synopsys, Cadence, or Siemens EDA.
* Expertise in Physical Layout Verification is required, including ownership and debugging of LVS, DRC, ERC, Antenna, and PERC signoff checks on complex SOC and mixed-signal designs.
* Experience with Siemens Calibre verification flows and RC extraction using StarRC and/or Calibre xACT is highly preferred.
* Experience with Git-based development flows is an advantage.
* Experience in IC design and/or verification is an advantage.
* Service-oriented, self-motivated, and possessing strong analytical and problem-solving skills.
* B.Sc. / M.Sc. in Computer Science, Electrical Engineering, or a related field from a leading institute.
* Strong programming and scripting skills in C / C ++, TCL, Python, and Linux shell scripting.
* Experience leveraging Generative AI tools for software development, automation, and productivity enhancement.
* Solid understanding of IC design and verification flows, with at least 5 years of hands-on experience using semiconductor EDA tools from Synopsys, Cadence, or Siemens EDA.
* Expertise in Physical Layout Verification is required, including ownership and debugging of LVS, DRC, ERC, Antenna, and PERC signoff checks on complex SOC and mixed-signal designs.
* Experience with Siemens Calibre verification flows and RC extraction using StarRC and/or Calibre xACT is highly preferred.
* Experience with Git-based development flows is an advantage.
* Experience in IC design and/or verification is an advantage.
* Service-oriented, self-motivated, and possessing strong analytical and problem-solving skills.
This position is open to all candidates.
